In present semiconductor technology, CMOS devices, such as nFETs or pFETs, are typically fabricated upon semiconductor wafers, such as Si, that have a singe crystal orientation. In particular, most of today's semiconductor devices are built upon Si having a (100) crystal orientation.
Electrons are known to have a high mobility for a (100) Si surface orientation, but holes are known to have a high mobility for a (110) surface orientation. That is, hole mobility values on (100) Si are roughly 2×-4×lower than the corresponding electron mobility for this crystallographic orientation. To compensate for this discrepancy, pFETs are typically designed with larger widths in order to balance pull-up currents against the nFET pull-down currents and achieve uniform circuit switching. pFETs having larger widths are undesirable since they take up a significant amount of chip area.
Hole mobility on (110) Si is 2×higher than on (100) Si; therefore, pFETs formed on a (110) surface will exhibit significantly higher drive currents than pFETs formed on a (100) surface. Unfortunately, electron mobility on (110) Si surfaces is significantly degraded compared to (100) Si surfaces.
As can be deduced from the above, the (110) Si surface is optimal for pFET devices because of excellent hole mobility, yet such a crystal orientation is completely inappropriate for nFET devices. Instead, the (100) Si surface is optimal for nFET devices since that crystal orientation favors electron mobility.
Hybrid oriented substrates having planar surfaces with different crystallographic orientation have recently been developed. See, for example, U.S. Patent Application Publication No. 2004/0256700 A1 and U.S. Pat. No. 7,023,055. Additionally, hybrid-orientated metal oxide semiconductor field effect transistors (MOSFETs) have recently demonstrated significantly higher circuit performance at the 90 nm technology node. As discussed above, the electron mobility and hole mobility can be optimized independently by placing the nFET on a (100) surface and the pFET on a (110) surface.
Although hybrid oriented substrates having planar surfaces of different crystal orientation can increase the carrier mobility, further improvement is needed in order to keep the performance scaling as devices are being scaled.
Another means to enhance carrier mobility is to introduce a stress into the channel of a MOSFET. Stress can be introduced into a single crystal oriented substrate by several methods including, for example, forming a stress inducing layer on top of the substrate and around the gate region. Although stress inducing layers can be used as a means to enhance carrier mobility, further improvement is still needed.
MOSFET structures have been proposed to have stressed channels on a hybrid oriented substrate. See, for example, U.S. Patent Application Publication No. 2006/0145264 A1. However, current substrate preparation for hybrid orientation (HOT) has a mixed substrate, SOI for nFETs and bulk for pFETs or vise versa. This would require the modification of circuit design due to different types of substrates for nFETs and pFETs.
U.S. Patent Application Publication No. 2005/0116290 A1 discloses a method utilizing localized amorphization and recrystallization of stacked template layers for fabricating a planar substrate having semiconductor layers of different crystallographic orientations. In particular, the '290 publication provides a means for fabricating a planar hybrid-orientation semiconductor-on-insulator (SOI) substrate structure comprising: at least two clearly defined single crystal semiconductor regions with different surface orientations, said at least two clearly defined single crystal semiconductor regions disposed on a common buried insulating layer, said common buried insulating layer disposed on a substrate.
In view of the drawbacks mentioned above with prior art techniques for improving the carrier mobility, there is still a need for providing a technique that is able to enhance the carrier mobility beyond that which can be achieved utilizing either hybrid oriented substrates, or stress inducing layers, and on a single SOI or bulk substrate.